The escalating requirements for high density and performance associated with ultra large-scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the sub-micron-features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed inter-metal dielectric layers and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the inter-metal dielectric layer separating the metallization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and microminiaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization levels is known as “damascene”-type processing. Generally, this process involves forming a via opening in the inter-metal dielectric layer or inter-layer dielectric (ILD) between vertically spaced metallization levels which is subsequently filled with metal to form a via electrically connecting the vertically spaced apart metal features. The via opening is typically formed using conventional lithographic and etching techniques. After the via opening is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques, and the excess conductive material on the surface of the inter-metal dielectric layer is then typically removed by chemical-mechanical planarization (CMP).
A variant of the above-described process, termed “dual damascene” processing, involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The opening is then filled with a conductive material to simultaneously form a contact or via in contact with a conductive line. Excess conductive material on the surface of the inter-metal dielectric layer is then removed by CMP. An advantage of the dual damascene process is that the contact or via and the upper line are formed simultaneously.
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the sub-micron range, step coverage problems may result from the use of Al. Poor step coverage causes high current density and enhanced electromigration.
One approach to improved interconnection paths in vias involves the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for the metallization level and W plugs for interconnections between the different metallization levels. The use of W, however, is attendant with several disadvantages. For example, most W processes are complex and expensive. Furthermore, W has a high resistivity, which decreases circuit speed. Moreover, Joule heating may enhance electromigration of adjacent Al wiring. Still a further problem is that W plugs are susceptible to void formation, and the interface with the metallization level usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem involves depositing Al using chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The use of CVD for depositing Al is expensive and hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization levels. Cu and Cu-based alloy metallization systems have very low resistivities, which are significantly lower than W and even lower than those utilizing Al and its alloys. Additionally, Cu has a higher resistance to electromigration. Furthermore, Cu and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver (Ag) and gold (Au). Also, in contrast to Al and refractory-type metals (e.g., titanium (Ti), tantalum (Ta) and W), Cu and its alloys can be readily deposited at low temperatures formed by well-known “wet” plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of manufacturing throughput.
Electroless plating of Cu generally involves the controlled auto-catalytic deposition of a continuous film of Cu or an alloy thereof on a catalytic surface by the interaction of at least a Cu-containing salt and a chemical reducing agent contained in a suitable solution, whereas electroplating comprises employing electrons supplied to an electrode (comprising the surface(s) to be plated) from an external source (i.e., a power supply) for reducing Cu ions in solution and depositing reduced Cu metal atoms on the plating surface(s). In either case, a nucleation/seed layer is required for catalysis and/or deposition on the types of substrates contemplated herein. A physical vapor deposition technique, such as sputtering, is useful for depositing the nucleation/speed layer.
Another technique to increase the circuit speed is to reduce the capacitance of the inter-metal dielectrics. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the R×C product, the more limiting the circuit speed. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the performance of multi-level interconnects is dominated by interconnect capacitance at deep sub-micron regimes, e.g., less than about 0.12 micron.
The dielectric constant of materials conventionally employed in the manufacture of semiconductor devices for an ILD ranges from about 3.9 for dense silicon dioxide to over 8 for deposited silicon nitride. The value of the dielectric constant expressed herein is based upon a value of one for a vacuum. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permittivity have been explored. The expression “low-k” material has evolved to characterize materials with a dielectric constant less than about 3.9.
One type of low-k material that has been explored are a group of flowable oxides which are basically ceramic polymers, such as hydrogen silsesquioxane (HSQ). HSQ-type flowable oxides have been considered for gap filling between metal lines because of their flowability and ability to fill small openings. HSQ-type flowable oxides have been found to vulnerable to degradation during various fabrication steps, including plasma etching.
HSQ typically contains between about 70% and 90% Si—H bonds. However, upon exposure to an O2-containing plasma, a considerable number of Si—H bonds are broken and Si—OH bonds are formed. Upon treatment with an O2-containing plasma, as much as about 20% to about 30% of the Si—H bonds in the deposited HSQ film remained. In addition, it was found that exposure to an O2-containing plasma increased the moisture content of the as deposited HSQ film and its propensity to absorb moisture. An HSQ film having a high Si—OH bond content tends to absorb moisture from the ambient, which moisture outgases during subsequent barrier metal deposition. Thus, it was found that during subsequent barrier and metal deposition. e.g. titanium-nitride and tungsten, outgassing occurred thereby creating voids leading to incomplete electrical connections.
Spin-on-glass (SOG) is also being used to obtain low-k dielectric layers, which can be fabricated at low temperatures. Silicates (Si(OH)4), siloxanes ((RO)nSi(OH)4-n) and silsesquioxanes (HSiO1.5)n are widely used for SOG materials. Silicates and siloxanes are generally mixed with an alcohol-based solvent such as methanol, ethanol, propanol, butanol, pentanol, hexanol, methylcellosolve, butylcellosolve, propylene glycol, diethylene glycol, or carbinol.
An SOG layer is generally formed on the semiconductor substrate by coating the SOG material mixed with one or more of the above-described solvents on a semiconductor substrate, and then rotating the substrate to uniformly distribute the material. The SOG material in a liquid state can fill grooves or trenches in the substrate to thereby planarize the substrate.
The solvent is generally evaporated by baking. The evaporated solvent and a carbon component generated from the solvent are generally degassed at approximately 100° C. to 400° C. The SOG layer is then thermally cured at temperatures of 400° C. or higher. In particular, the silicate or siloxane material is heated so that silanol (Si—OH) groups in the materials can produce H2O and cross-link to form a Si—O—Si network, thereby resulting in a solid SOG layer with properties similar to those of conventional SiO2 layers. As a result of the heat treatment, the SOG layer undergoes a change in its index of refraction.
When the siloxane or silicate material is heated, water is generally produced. Accordingly, the volume of the SOG layer is generally reduced during the curing process. Also, the siloxane SOG generally includes some alkyl groups at the position of the silanol group, so that the area of cross-linking may be reduced, to thereby cause less volume reduction. Further, the heat treating process may generate stress in the SOG layer and thereby cause cracks therein. Siloxane SOG may have good crack resistance when it is thickly coated. Silicate SOG is generally more rigid and may create cracks during heat treatment, even when thickly coated.
The SOG heat treating process generally uses a furnace, oven, or hot plate. For example, the semiconductor substrate is heat treated at a temperature below 350° C. on a hot plate, and is then heat-treated above 400° C. in a furnace. However, thermally curing the dielectric film increases thermal stresses in the dielectric film and can damage the semiconductor device. Electrical contacts, such as NiSi contacts, which are sensitive to high temperatures, are susceptible to damage during dielectric thermal curing.
SOG layers may also be hygroscopic. When moisture is absorbed due to hygroscopicity, the cross-linking may be destroyed and thereby adversely impact the properties of the SOG layer. In particular, as the hygroscopicity increases, the dielectric property of the SOG insulating layer may decrease. Accordingly, it is desirable to reduce or eliminate the problems with cracking and hygroscopicity in SOG layers.
Additional problems may be created when SOG is used. A poison via phenomenon may take place wherein the SOG material, which is exposed on the via sidewall, may cause an increase in the contact resistance. In particular, the poison via phenomenon can occur due to outgassing of the SOG. It is known that the poison via phenomenon may be caused by the silanol group in the SOG material. For example, when an Al layer is deposited on the Si—OH group, an oxide layer of Al2O3 may be formed, which thereby increases the contact resistance.
Another approach has been to employ nanoporous silica, which can have dielectric constants for bulk samples in the range of 1 to 3. Nanoporous silica is attractive because it employs similar precursors as used for SOG and CVD SiO2 and because of the ability to carefully control pore size and pore size distribution. In addition to having a low dielectric constant, nanoporous silica offers other advantages for microelectronics including thermal stability up to at least 500° C., small pore size, the ability to tune the dielectric constant over a wide range, and deposition using similar tools as employed for conventional SOG processing. Density is the key nanoporous silica parameter controlling property of importance for dielectrics. Properties of nanoporous silica may be varied over a continuous spectrum from the extremes of an air gap at a porosity of 100% to dense silica with a porosity of 0%. As density increases, dielectric constant and mechanical strength increase but the pore volume decreases. Density is dependent on pore volume or porosity for given material. The optimal porous material should be compromise between mechanical strength and dielectric constant.
Nanoporous dielectric silica coatings can be formed by depositing a mixture of liquid alkoxysilane precursor composition in a solvent onto a spinning silicon wafer substrate to thereby coat the substrate. The coating is typically polymerized, condensed, and cured to form a nanoporous dielectric silica coating on the substrate. Nanoporous films can also be deposited using CVD methods. One example is a CVD SiCOH film in which the SiCOH precursor is mixed with a porogen chemical. The porogen is incorporated into the CVD film, and it can be removed later using thermal, e-beam, UV, or microwave curing.
SiCOH, which exhibits a dielectric constant of about 2.4 to about 3.1, contains carbon in the amount of about 5 to about 20 atomic %, silicon in the amount of about 15 to about 25 atomic %, oxygen in the amount of about 25 to about 35 atomic %, and hydrogen in the amount of about 35 to about 45 atomic %. SiCOH contains SiC, SiH, CH, and SiOH bonding.
Nanoporous silica films are principally composed of silicon and oxygen in which there are pores distributed throughout the material. The pores range in size from about 0.1 nm to 100 nm. Nanoporous silica films can be used provided that silanol groups and water are excluded from the film. Silanols and water will raise the dielectric constant of the film because they are highly polarizable in an electric field. To make nanoporous film substantially free of silanols and water, an organic reagent such as hexamethyldisilazane or methyltriacetoxysilane, is optionally introduced into the pores of the film. This reagent reacts with silanols on the pore surfaces to form trimethylsilyl groups. The latter serve to mask the silanol groups and to make the film hydrophobic. A drawback to the use of trimethylsilyl group is that the film is no longer pure SiO2. Carbon and hydrogen content may be as high as 10% by weight.
Oxidizing plasmas will readily oxidize trimethylsilyl groups from nanoporous films and this will lead to the formation of water and silanols. In addition, oxidized silica films will easily absorb water from conductive manufacturing environments. The retention of water and silanols as a result of oxidation and or absorption of water from manufacturing environments causes two problems: a significant increase in dielectric constant and difficulty in forming low resistance metal vias (the poison via problem).
Alternative methods of curing have been proposed for curing low-k dielectric film such as electron beam and ultraviolet irradiation. However, electron beam irradiation causes damage to transistors and ultraviolet curing does not increase the mechanical strength as much as electron beam, thus thermal curing may still be required to obtain acceptable mechanical properties.
Porosity and pore size of the dielectric film can be controlled by the adding porogens to the nanoporous and other low-k dielectric films. Porogens are organic compounds that are thermally volatilized during the curing process to create pores in the dielectric film. The porogen undergoes phase separation during the thermal cure of a dielectric/porogen mixture. The phase separated porogen collects in nanoscopic domains within the host material and thermally decomposes into volatile by-products (i.e.—porogen fragments) that diffuse out of the low-k dielectric leaving pores in their place. Dow Chemical's porous SiLK™ product and JSR Corporation's JSR 5109 product are examples of commercially available low-k dielectric precursors containing porogens.
Thus, it would be desirable to produce a nanoporous silica film which has a dielectric constant ≦2.5, which contains low levels of water and which is stable to oxygen plasma as well to other chemical solvents used in semiconductor manufacturing. It would further be desirable to more efficiently form stronger dielectric films with controlled pore sizes and with improved adhesion of the dielectric film to adjoining layers of the semiconductor device.